Conventional semiconductor memory devices are classified as volatile or non-volatile memory devices. Volatile memory devices include memory devices such as DRAM, SRAM and the like. Non-volatile memory devices include memory devices such as PROM, EPROM, EEPROM, MRAM, FRAM, flash EEPROM, etc. A volatile memory devices loses stored data at power-off, whereas a non-volatile memory device retains stored data even without power. Flash memory devices such as EEPROM (electronically erasable and programmable read only memory) may be used as a storage medium in various applications and devices (such as computer systems), in which there is a possibility that power is interrupted. Flash memory devices may have relatively fast programming speeds and/or lower power consumption. Conventional flash memory devices such as NAND flash memory devices may also have a relatively high level of integration.
A conventional NAND flash memory device includes EEPROM memory cells referred to as flash EEPROM cells or flash memory cells. A conventional flash memory cell includes a cell transistor, which has a semiconductor substrate (or bulk), source and drain regions spaced apart from each other, a floating gate arranged on a channel region between the source and drain regions and storing electrons, and a control gate arranged on the floating gate. An example array of a conventional NAND flash memory device including such cell transistors is illustrated in FIG. 1. The conventional array of FIG. 1 includes a plurality of cell strings (or NAND strings), each of which may be configured in the same manner.
Referring to FIG. 1, a cell string includes a string select transistor SST as a first select transistor, a ground select transistor GST as a second select transistor and a plurality of (e.g., 32) memory cells MC0-MC31 connected in series between the select transistors SST and GST. In each cell string, the string select transistor SST has a drain connected to a corresponding bit line and a gate connected to a string select line SSL. The ground select transistor GST has a source connected to a common source line CSL and a gate connected to a ground select line GSL. The memory cells MC0-MC31 are serially connected between a drain of the ground select transistor GST and a source of the string select transistor SST. Gates of each of memory cells MC0-MC31 are connected to a corresponding one of word lines WL0-WL31.
A group of cell strings such as those illustrated in FIG. 1 is also referred to as a memory block. In a conventional NAND flash memory device, program and read operations are made by page unit, and erase operations are carried out per block unit. Conventionally, prior to a program operation, memory cells may be erased and set to a threshold voltage lower than 0V.
FIG. 2 illustrates a conventional erase method. As shown, the conventional erase method may include performing an erase operation (S10) and performing an erase verify operation (S20). At S10, all memory cells in a memory block are erased simultaneously. For example, as illustrated in FIG. 3, memory cells are simultaneously erased by driving word lines WL0-WL31 in a memory block with a voltage of 0V and a substrate (or a bulk) with an erase voltage Verase (e.g., 19V). At this time, the string and ground select lines SSL and GSL are floating. With this bias condition, electrons are discharged from a floating gate into the substrate (or bulk). At S20, whether threshold voltages of erased memory cells are lower than a target threshold voltage is verified. For example, as illustrated in FIG. 4, a sense current is supplied to bit lines from a page buffer circuit (not shown). For example, a voltage of 0V is applied to word lines WL0-WL31 in a memory block, and a read voltage Vread is applied to the string and ground select lines SSL and GSL. With this bias condition, when threshold voltages of all memory cells reach a target threshold voltage or lower than the target threshold voltage, the sense current supplied to the bit lines is discharged to a common source line CSL through a cell string. In the event that a threshold voltage of at least memory cell does not reach the target threshold voltage, the sense current is not discharged to the common source line through a cell string.
After applying the sense current, an erase pass/fail may be determined by sensing a potential on respective bit lines. When the result indicates erase fail, the S10 and S20 may be repeated until the result indicates an erase pass.
The above-described conventional erase verify method is disclosed in U.S. Pat. No. 6,009,014 entitled “ERASE VERIFY SCHEME FOR NAND FLASH,” the entire contents of which are incorporated herein by reference.
Improving the degree of integration of conventional NAND flash memory devices may decrease the space between signal lines such as word lines, a string select line and/or a ground select line. The decrease in space between word lines may be proportional to the improvement in the degree of integration, while the decrease in space between a select line(s) and an adjacent word line may not be proportional to the improving degree of integration. For example, as illustrated in FIG. 5, a space S2 between a string select line SSL and an adjacent word line WL31 is wider than the space S1 between word lines WL0 and WL1 due to program disturbance. When a relatively high voltage is applied to word line WL31 (e.g., during a program operation), a voltage of the string select line SSL may increase. This may cause a string select transistor in a string including a program-inhibited cell to turn-on and a channel voltage of the program-inhibited cell may be discharged to a bit line via the turned-on string select transistor. For at least this reason, reducing the space S2 between a select line SSL and word line WL31 to be the same or substantially the same as the space S1 between word lines may be relatively difficult.
Still referring to FIG. 5, for example, if the spaces S1 and S2 are different from each other, a source/drain junction resistance of a memory cell transistor in respective word lines WL0 and WL31 may be changed. A halo process in which a p-type impurity region is formed below n-type source and drains of each cell transistor may be used to reduce short channel occurrences caused by improving the degree of integration. This p-type impurity region, as illustrated in FIG. 6, may be formed by injecting boron ions in a substrate at an angle of 7° to 8°. Because the space S2 is wider than the space S1, boron may be injected at source/drain junctions placed between a string select line SSL and word line WL31 and between a ground select line GSL and word line WL0. This may vary the source/drain resistance according to a variation of a voltage (e.g., 0V or a read voltage) applied to word line WL0/WL31. Accordingly, a cell current flowing via a memory cell connected to the word line WL0/WL31 may vary according to a voltage variation (e.g., 0V or a read voltage) applied to word line WL0/WL31.
In addition, in the above-described conventional structure, threshold voltages of erased memory cells are distributed more widely. In this example, when an erase operation is performed, a voltage of 0V is applied to word lines WL0-WL31 and an erase voltage Verase is applied to a substrate (or bulk). Because string and ground select lines SSL and GSL are floating, when the erase voltage Verase is applied to the substrate (or bulk), voltages of the lines SSL and GSL are boosted. As a result, potentials of floating gates connected to the word lines WL0 and WL31 may be higher than those of memory cells connected to remaining word lines WL1-WL30 due to the voltage increase of the select lines SSL and GSL.
As illustrated in FIG. 7, for example, in the case of a memory cell in word line WL1, a potential of a floating gate (marked by FG(WL1)) of a memory cell may be determined based on coupling capacitances C1, C2 and C3 between word lines WL0, WL1 and WL2 and the floating gate FG(WL1) and a coupling capacitance C4 between a substrate and the floating gate FG(WL1). Although not shown, a specific voltage may be induced in the same manner at a floating gate of a memory cell connected to respective word lines WL2-WL30. On the other hand, in the case of a memory cell in word line WL0, a potential of a floating gate (marked by FG(WL0)) of a memory cell may be determined based on coupling capacitances C11, C12 and C13 between select and word lines GSL, WL0 and WL1 and the floating gate FG(WL0) and a coupling capacitance C14 between a substrate and the floating gate FG(WL0). Although not shown, a specific voltage may be induced in the same manner at a floating gate of a memory cell connected to a word line WL31.
Herein, in case of a conventional NAND flash memory device, a substrate where memory cells are formed may include a pocket p-well, which is formed within a deep n-well formed at a p-type substrate. Such a triple well structure is disclosed in U.S. Pat. No. 5,962,888 entitled “WELL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME,” the entire contents of which are incorporated herein by reference.
As voltages of the string and ground select lines SSL and GSL are boosted, voltages of floating gates of memory cells connected to word lines WL0 and WL31 may increase due to boosted voltages of the string and ground select lines SSL and GSL. As a result, an electric field generated between a substrate and floating gates of memory cells connected to word lines WL0 and WL31 may decrease. Due to the reduction of electric field between a substrate and floating gates, an erase speed of memory cells connected to word lines WL0 and WL31 may become slower than that of memory cells connected to remaining word lines WL1-WL30. As a result, as illustrated in FIG. 8, in conventional NAND flash memory devices, threshold voltages of erased memory cells are more widely distributed due to memory cells connected to word lines WL0 and WL31. If a threshold voltage distribution of erased memory cells is widened due to memory cells connected to word lines WL0 and WL31, as illustrated in FIG. 8, a threshold voltage distribution of programmed memory cells is also widened. Further, memory cells connected to the word lines WL0 and WL31 may cause an increase in an erase loop number, which may increase erase time. This may result in erase fails in memory cells.